Stand-Alone Ethernet Controller

      Release Time：07/07/2016
    FEATURES                                   
                  n5X5 mm, 32-pin QFN
                  nCompatible with Motorola SPI SPEC
                  lInput clock frequency up to 60MHz
                  lOnly support phase 0
                  lOnly support polarity 0
                  nIEEE 802.3 compatible Ethernet controller
                  nFully compatible with 10/100 BASE-T networks
                  nIntegrated MAC and 10/100 PHY
                  nSupports full and half duplex modes
                  nProgrammable padding and CRC
                  generation
                  nProgrammable padding and CRC stripping
                  nProgrammable flow control
                  nSupports Ethernet frame length up to 1522 bytes
                  nFlexible address filtering modes
                  n8k byte receive buffer
                  n4k byte transmit buffer
                  nMulti-function LED output
                  n2.8V IO supply and 1.2V core supply
                  nCMOS process technology
     
     2 ORDER INFORMATION                                   
    Order Number
    Temperature Range
    Package
    Marking
    Packing Type
    AW6688TQR
    -40~85℃
    TRQ5x5-32L
    AW6688
    Tape & Reel
     
     
    3 OVERVIEW                                    
    AW6688 is a standalone SPI to Ethernet converter which serves as an Ethernet network interface for any controller with SPI master interface. The SPI interface is fully compatible with MOTO SPI interface SPEC and only supports phase 0 and polarity 0 of the SPI clock. The clock rate of the SPI interface is up to 60MHz. A dedicated interrupt output is used to communicate with the SPI master chip. The Ethernet interface of AW6688 is fully compatible with IEEE802.3 protocol. A number of embedded filters are used to limit the incoming Ethernet packets. Integrated hardware CRC calculator helps to release the CPU power of the master. A 4k byte transmit buffer and an 8k byte receive buffer is integrated. Stream mode of transferring the Ethernet packets through the SPI interface is supports under which the SPI transfer boundary can be at any word boundary of the Ethernet packets. The block diagram of the chip is shown below.
              Figure 1 AW6688 block diagram
     
     The function of the major block of AW6688 is listed below: MACspi_ifFrame dectx_fiforx_fifospi_regclk & rstspi_if_toprx data fifotx data fifotx stat fifoReg interfacePHY
                  nSPI_IF: the SPI_IF serves as the SPI protocol decoder and serial to parallel converter.
                  nTX_FIFO, RX_FIFO: the FIFO servers as the synchronizer between the SPI clock domain and the system clock domain.
                  nFRAME_DEC: the FRAME_DEC decodes and encodes the SPI packet, performs the register programming, recognizes the Ethernet packets and performs the data transfer between the internal data FIFO.
                  nSPI_REG: all the SPI related registers and the interrupt related logic are implemented in the SPI_REG
                  nMAC: the MAC implements the IEEE802.3 compliant MAC logic.
                  nPHY: the PHY performs the data transfer between the analog interface and the MAC